SOC Design Engineer

Company: Intel
Location: Pflugerville
Posted on: January 19, 2023

Job Description:

Job Description
The Custom Structured ASIC Engineering Group within Intel Programmable Solutions Group is seeking a versatile and talented candidate to be part of Intel's next generation Custom Structured ASIC Development Team.
In this position, you will Architect and Design CPU Subsystems powering the next generation Structured ASIC products. You will be part of a skilled team Designing and Validating the Configuration engines for multiple SOCs. To support increased coverage for our Subsystem, you will develop Hardware Emulation RTL models for our products reducing significantly the validation time. This is an opportunity to actively collaborate across Design Engineering, Validation, Architecture, and Firmware Teams to provide the most optimal solutions.
In this role your responsibilities will include but not limited to:

• Write RTL code that can efficiently interface the device peripherals
• Design for reusability; the RTL should be easily customizable through parameters, pass all the front-end design quality metrics, and have supporting documentation
• Develop a set of metrics to assess the performance (power, throughput, latency) of the subsystems in different use cases
• Work with Firmware Developers to create testcases targeting the critical functions of each subsystem
• Document the complete functionality and work with the Chip Architecture Team to cover all the uses cases
• Develop the timing constraints and work with the Implementation Team to identify the bottlenecks in the flow
• Work closely with the DFT Team for efficient test insertion with minimum performance degradation
• Define and develop simplified RTL models of the Full Chip for HW Emulation to support Validation Team efforts in reducing the runtime and increase test coverageA successful candidate will demonstrate:
  • Good problem-solving skills and debugging capabilities
  • Good communication skills and teamwork
  • Highly motivated self-starter, willing to work in a collaborative environment with cross-organizational teams as well as independently
    Qualifications
    Minimum Qualifications:
    • Bachelors or MS degree in Computer Science, Computer Engineering, or Computational Science
    • Advanced experience with chip design and verification flow
    • Minimum 5 years of experience in Chip Design, Implementation, or Verification
    • Advanced experience of Verilog, System Verilog, or VHDL
    • Experience with one or more scripting languages like Python, TCL or PERL
      Preferred Qualifications:
      • Experience with different CPU Architectures is a big plus
      • Experience with Hardware Emulation Platforms
      • Experience in Chip Design Implementation and SDC Development
      • Experience with Debug Interfaces (mainly JTAG) is considered a big plus
      • Familiarity with Control Revision Systems such as GIT or Perforce
        Inside this Business Group
        The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies-spanning software, processors, storage, I/O, and networking solutions-that fuel cloud, communications, enterprise, and government data centers around the world.
        Other Locations
        US,OR,Hillsboro;US,TX,Austin;US,AZ,Phoenix;US,CA,Folsom
        Covid Statement
        Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
        Posting Statement
        All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
        Benefits
        We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
        Annual Salary Range for jobs which could be performed in US, California: $139,480.00-$209,760.00
        *Salary range dependent on a number of factors including location and experience
        Working Model
        This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Keywords: Intel, Pflugerville , SOC Design Engineer, Engineering , Pflugerville, Texas